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What is testbench top module ?

1. Event Taps Testbench Design
2. Event Taps Testbench Free
3. Event Taps Testbench System
4. Event Taps Testbench Cost

The testbench creates some signals to connect the stimulus to the Device Under Test (DUT) component. The DUT is the FPGA’s top level design. In our case examplevhdl. (examplevhdl is the top level entity of our FPGA design) Quartus examplevhdl.vhd (top level design file) examplevhdl.vht (testbench file) Top level entity becomes a.

All verification components, interfaces and DUT are instantiated in a top levelmodule called testbench. It is a static container to hold everything required to be simulated and becomes the root node in the hierarchy. This is usually named tb or tb_top although it can assume any other name.

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Simulators typically need to know the top level module so that it can analyze components within the top module and elaborate the design hierarchy.

Click here to know more about top level modules !

Testbench Top Example

The example below details the elements inside the top module tb_top.

Note the following :

• tb_top is a module and is a static container to hold everything else
• It is required to import uvm_pkg in order to use UVM constructs in this module
• Clock is generated in the testbench and passed to the interface handle dut_if1
• The interface is set as an object in uvm_config_db via set and will be retrieved in the test class using get methods
• The test is invoked by run_test method which accepts name of the test class base_test as an argument
• Call waveform dump tasks if required

Clock generation

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A real design may have digital blocks that operate on multiple clock frequencies and hence the testbench would need to generate multiple clocks and provide as an input to the design. Hence clock generation may not be as simple as an always block shown in the example above. In order to test different functionalities of the design, many clock parameters such as frequency, duty cycle and phase may need to be dynamically updated and the testbench would need infrastructure to support such dynamic operations.

The approach shown above may not be scalable and need to be driven from the testbench using hierarchical signal paths since they are instantiated as modules. A better UVM alternative is to create an agent for the clock so that it can be easily controlled from sequence and tests using agent configuration objects.

Reset Generation

In a similar way, a reset agent can be developed to handle all reset requests. In many systems, there are two kinds of reset - hardware and software. A software reset is typically done through a register model and would be separate from a reset agent. Hardware resets include assertion of the system reset pin for a given duration or follow a certain sequence of events before the actual reset is applied. All such scenarios can be handled separately using this reset agent which needs a handle to the reset interface.

Creation of internal tap points

Some testbench components may rely on tapping internal nets in the design to either force or sample values to test certain features. These internal nets may need to be assigned to a different value based on input stimuli and can be done so in the top level testbench module. Such signals can be tied to a generic interface and be driven from another agent.

Learn how run_test() starts the actual UVM test from this blog post.

Stimulus API¶

Below is a list of ClockDomain stimulation functions:

ClockDomain stimulus functions	Description
forkStimulus(period)	Fork a simulation process to generate the clockdomain stimulus (clock, reset, softReset, clockEnable signals)
forkSimSpeedPrinter(printPeriod)	Fork a simulation process which will periodically print the simulation speed in kilo-cycles per real time second. printPeriod is in realtime seconds
clockToggle()	Toggle the clock signal
fallingEdge()	Clear the clock signal
risingEdge()	Set the clock signal
assertReset()	Set the reset signal to its active level
deassertReset()	Set the reset signal to its inactive level
assertClockEnable()	Set the clockEnable signal to its active level
deassertClockEnable()	Set the clockEnable signal to its active level
assertSoftReset()	Elektrina d.o.o driver download for windows. Set the softReset signal to its active level
deassertSoftReset()	Set the softReset signal to its active level

Wait API¶

Below is a list of ClockDomain utilities that you can use to wait for a given event from the domain:

ClockDomain wait functions	Description
waitSampling([cyclesCount])	Wait until the ClockDomain makes a sampling, (active clock edge && deassertReset && assertClockEnable)
waitRisingEdge([cyclesCount])	Wait cyclesCount rising edges on the clock; cycleCount defaults to 1 cycle if not otherwise specified. Note, cyclesCount = 0 is legal, and the function is not sensitive to reset/softReset/clockEnable
waitFallingEdge([cyclesCount])	Same as waitRisingEdge but for the falling edge
waitActiveEdge([cyclesCount])	Same as waitRisingEdge but for the edge level specified by the ClockDomainConfig
waitRisingEdgeWhere(condition)	Same as waitRisingEdge, but to exit, the boolean condition must be true when the rising edge occurs
waitFallingEdgeWhere(condition)	Same as waitRisingEdgeWhere, but for the falling edge
waitActiveEdgeWhere(condition)	Same as waitRisingEdgeWhere, but for the edge level specified by the ClockDomainConfig

Warning

All the functionalities of the wait API can only be called from inside of a thread, and not from a callback.

Callback API¶

Below is a list of ClockDomain utilities that you can use to wait for a given event from the domain:

ClockDomain callback functions	Description E.digital driver download for windows.
onNextSampling{callback}	Execute the callback code only once on the next ClockDomain sample (active edge + reset off + clock enable on)
onSamplings{callback}	Execute the callback code each time the ClockDomain sample (active edge + reset off + clock enable on)
onActiveEdges{callback}	Execute the callback code each time the ClockDomain clock generates its configured edge
onEdges{callback}	Execute the callback code each time the ClockDomain clock generates a rising or falling edge
onRisingEdges{callback}	Execute the callback code each time the ClockDomain clock generates a rising edge
onFallingEdges{callback}	Execute the callback code each time the ClockDomain clock generates a falling edge

Default ClockDomain¶

You can access the default ClockDomain of your toplevel as shown below:

Note that you can also directly fork a standard reset/clock process:

An example of how to wait for a rising edge on the clock:

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New ClockDomain¶

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If your toplevel defines some clock and reset inputs which aren’t directly integrated into their ClockDomain, you can define their corresponding ClockDomain directly in the testbench: